Hyperscaler Power Constraints — POET's Limited Direct Exposure

Confidence legend: ✓ verified-primary · ◐ partial / aggregator · ⚠ inferred / estimate.

Important framing note: Power-per-bit is one of the dominant secular tailwinds in the silicon-photonics narrative. For MRVL (whose Polariton acquisition delivers plasmonic-organic-hybrid modulators with materially lower drive voltage) and for LWLG (whose entire EO-polymer thesis rests on improved power-per-bit at high data rates), the power-wall narrative is directly load-bearing for the company-specific investment thesis. For POET, the power-wall narrative is less directly relevant. POET’s Optical Interposer is a packaging-integration technology — a passive silicon waveguide substrate that mounts III-V active devices via flip-chip bonding, packaged at the wafer level. The platform does not produce a fundamentally lower-power modulator; the modulator/laser physics are determined by the III-V devices that are mounted on the interposer, not by the interposer architecture itself. This page is honest about that limited direct readthrough while documenting the indirect demand-side flow-through. POET-specific power-related claims should be flagged as ⚠ inferred unless the 20-F or a press release explicitly addresses power efficiency.

1. The power-per-bit narrative — what is the secular driver

Datacenter operators face a structural constraint: electrical power available to a given datacenter site is finite (limited by grid interconnect capacity, transformer ratings, cooling capacity). As GPUs scale (NVIDIA Blackwell ~700W TDP, expected Rubin family in 1-2kW range), the fraction of the power budget available for networking shrinks unless networking power-per-bit improves.

Industry data points

Hyperscaler power-budget allocation: Approximately 45-55% of datacenter power goes to compute (GPUs), 15-20% to networking, optics, and switching, with the balance going to memory, storage, cooling, and power conversion. ⚠ industry consensus
Optical-port power consumption: Current 800G transceivers operate at approximately 15W per port (ZR/ZR+ coherent), or 5-10W per port (PAM4 short-reach). 1.6T pluggables target ~20W per port at scale; CPO targets ~10W. ⚠ LightCounting / 650 Group industry estimates
Total optical-power share at hyperscaler scale: A typical hyperscaler datacenter rack has dozens to hundreds of optical ports. As port speeds scale 800G → 1.6T → 3.2T, port count per rack stays roughly flat but per-port power increases — leading to a structural increase in optical-power share unless per-bit power efficiency improves.

Why this matters for high-density optics generally

The aggregate power-wall pressure is the secular driver pulling higher-bandwidth-per-watt optical interconnect into datacenter buildouts. Three architectural responses are competing:

Lower-drive-voltage modulators (LWLG EO-polymer, Marvell-via-Polariton plasmonic-organic-hybrid, Lumentum thin-film lithium niobate) — directly reduces modulator drive power.
Co-packaged optics (CPO) — moves optics inside the switch ASIC package, eliminates electrical-link loss between switch and optics, reduces overall network power per bit.
Higher per-lane data rate (200G PAM4 today, 400G PAM4 by 2028, possibly 800G PAM4 thereafter) — fewer lanes per port = less aggregate power per port at the same total bandwidth.

POET’s Optical Interposer addresses none of these directly. The interposer is an integration / packaging architecture, not a modulator-physics innovation, not a CPO architecture, and not a per-lane-rate enabler.

The 20-F’s discussion of the Optical Interposer (Item 4.B) emphasizes assembly cost reduction and scalability, NOT power efficiency: “POET’s Optical Interposer eliminates costly components and labor-intensive assembly, alignment, and testing methods employed in conventional photonics. We believe the cost-efficient integration scheme and scalability of the POET Optical Interposer brings value to devices or systems that integrate electronics and photonics, including high-growth areas of communications and computing.” ✓ Form 20-F filed 2026-03-31, Item 4.B — direct quote

POET’s value claims are about:

Manufacturing cost (wafer-level assembly vs. discrete optics, lower labor cost)
Scalability (wafer-scale yield improvements vs. unit-level alignment)
Latency (the 20-F explicitly mentions “decreases in latency” as part of the AI-system requirement set, with the Optical Interposer positioned as a contributor)

The 20-F mentions “extraordinary demands on cloud-based AI service providers and hyperscale data centers for increases in network speeds and bandwidth and decreases in latency” — but does NOT mention power as a primary driver. ✓ Same source.

Where POET could (indirectly) help with power

There is a second-order argument that POET’s interposer indirectly improves power efficiency:

Tighter integration of laser + modulator + waveguide on a single substrate reduces optical insertion loss (less optical power needs to be generated to deliver the same received signal). Insertion-loss reduction translates to lower laser-pump power requirements.
Wafer-level assembly precision improves coupling efficiency between the III-V devices and the silicon waveguide, again reducing required laser-pump power.

These are modest power efficiency improvements (~5-15% range vs. discrete-optics packaging ⚠ industry consensus), not the order-of-magnitude improvements that the LWLG-EO-polymer or Polariton-POH narratives claim.

3. The indirect demand-side flow-through

While POET’s platform doesn’t directly reduce per-bit power, the secular power-wall narrative still flows through to POET via the demand-side channel:

Read-through: hyperscaler power constraints → high-density optical demand → POET

Hyperscalers facing power-budget constraints are pushing module makers to:

Adopt 1.6T pluggable optics earlier (8-lane 200G vs. 16-lane 100G — fewer lanes at the same bandwidth = lower aggregate power).
Demand integrated optical engines (vs. discrete optics) for density / form-factor reasons that allow more port-count per rack-unit at the same power budget.
Plan CPO transition starting 2027-2028 (which both reduces network power and allows higher rack-density).

Items 1 and 2 are direct demand drivers for POET’s product roadmap. Item 3 is a competitive headwind (CPO compresses POET’s merchant-pluggable monetization window).

POET’s 20-F framing of this demand vector

The 20-F’s customer-targeting language is: “module makers that are heavily focused on selling to hyperscale data centers actively implementing AI services.” ✓ Form 20-F filed 2026-03-31, Item 5.C

POET’s bet is that the merchant-pluggable transition to 1.6T will be driven by hyperscaler power-density pressure, and the form-factor advantages of POET’s wafer-level integration position it well for that transition.

4. Comparison with MRVL and LWLG power-narratives

Company	Power-narrative directness	Mechanism
LWLG	Direct, primary thesis	EO-polymer modulators with ~5-10× lower V-π·L vs. silicon Mach-Zehnder; orders-of-magnitude lower drive power at high data rates
MRVL (Polariton acquisition)	Direct, secondary thesis	Plasmonic-organic-hybrid modulators provide low-drive-voltage path to 3.2T+ scaling
POET	Indirect, tertiary thesis	Wafer-level integration density + form-factor benefits enable port-count scaling within a constrained power envelope; modulator physics unchanged

Investors importing the “power-wall thesis” framing from MRVL or LWLG analysis to POET are mis-modeling the magnitude of the readthrough. POET benefits from the same secular tailwind but with smaller per-deal economic uplift — POET’s value-add is on assembly cost and density, not on modulator drive voltage.

5. The CPO-displacement risk in detail

The bear scenario where the power-wall narrative actively HURTS POET is the accelerated CPO ramp. If hyperscaler power-budget pressure pulls CPO adoption earlier than current consensus (2027-2028 → 2026-2027), then merchant pluggable demand compresses sooner, compressing POET’s monetization window:

CPO ramp timing	Merchant pluggable TAM impact (2028E)	POET-specific impact
CPO ramp on consensus schedule (2027-2028 production)	-10% TAM compression by 2030	Limited; POET 1.6T monetization 2027-2029
CPO ramp earlier (2026-2027 production)	-25% TAM compression by 2030	POET 1.6T monetization window narrows to ~18 months
CPO ramp delayed (post-2029)	TAM continues +30% CAGR through 2030	POET 1.6T monetization extends through 2030

The current state of CPO development supports the consensus schedule:

NVIDIA Spectrum-X silicon-photonics co-packaged optics: announced 2025; full ramp 2027-2028. ◐
Broadcom Tomahawk-Ultra with CPO: shipped 2024 in limited deployments; volume 2026-2027.
Hyperscaler-specific CPO programs (Microsoft Maia + photonic integration; Google Apollo): in development, not yet at volume scale.

POET’s competitive frame is: win the 1.6T merchant-pluggable design-in cycle 2026-2028 before CPO compresses the window. The 20-F’s explicit 2026 strategic focus on 1.6T optical engines aligns with this timing. ✓ Form 20-F filed 2026-03-31, Item 5.C

6. Honest assessment summary

The power-per-bit narrative is a secular tailwind for high-density datacenter optics generally. POET benefits from this tailwind through the demand-side channel — hyperscaler power-budget pressure pulls 1.6T module adoption forward, expanding POET’s addressable design-in cycle.

POET’s Optical Interposer is NOT itself a power-reducing modulator architecture. Investors looking for an MRVL-Polariton-style or LWLG-style power-per-bit value-add at the platform level should look elsewhere (or expect modest indirect benefits via integration density / coupling efficiency).

The specific power-related risk for POET is accelerated CPO ramp. If hyperscaler power-pressure pulls CPO adoption earlier than 2027-2028, POET’s 1.6T merchant-pluggable monetization window compresses.

For analyst purposes:

Use the power-wall framing for demand-side context (TAM, capex direction, hyperscaler buying behavior).
Do NOT use the power-wall framing for POET-platform-specific value claims — those are about cost, density, and form-factor, not modulator physics.
Track CPO-ramp commentary from NVIDIA, Broadcom, hyperscaler quarterly calls — accelerated CPO is the bear case.

Cross-section pointers

ai capex cycle — Demand-side capex direction; the 1:1 read-through to module-maker order flow.
tam sam — TAM sensitivity to CPO-displacement timing.
industry dynamics — Module-maker landscape; explains why POET’s customer base (Innolight / Eoptolink) is most exposed to CPO timing.
overview — Technical detail on the Optical Interposer architecture; cross-reference for “what does POET actually deliver vs. claim.”
bear case — Bear-case scenario where accelerated CPO ramp compresses POET’s monetization window.