POET Optical Interposer — platform overview

Updated: 2026-04-29 Status: ✓ Verified via 20-F (FY2024, accession 0001641172-25-002143), POET technology page, ECOC 2025 technical paper, except where flagged Cross-references: Optical interconnect roadmap · Products · Foundry relationships · Patents · Papers and conferences · competitors

Executive summary

The POET Optical Interposer is a hybrid-integration platform that uses a passive silicon waveguide layer as a “circuit board for light,” onto which active III-V devices (lasers, electro-absorption modulators, photodiodes) and CMOS electronics (drivers, transimpedance amplifiers, multiplexers, DSPs) are flip-chip bonded in a single chip-scale assembly. The substrate is fabricated on standard 8-inch silicon wafers using semiconductor-foundry processes, which gives POET access to high-volume CMOS economics without owning a fab. ✓ (POET technology page)

The architectural bet is that the data-center optical-interconnect market — moving from 800G to 1.6T to 3.2T per port between 2025 and 2028 — needs three things at once: (1) higher integration density to fit more lanes into pluggable cages and co-packaged optics (CPO) substrates; (2) lower bill-of-materials cost than discrete TOSA/ROSA assemblies; and (3) sourcing flexibility for the active devices, because no single material system (silicon, indium phosphide, lithium niobate, EO polymer) wins every figure of merit. POET’s interposer is substrate-agnostic with respect to the active devices — any flip-chip-compatible III-V or LN chip can be bonded — which lets the company position the platform as a packaging IP licensable across material generations, rather than a bet on a specific gain medium. ✓ (POET 1.6T 2xFR4 transmitter blog post)

The principal architectural alternatives are: (a) monolithic silicon photonics (Intel SiPh, GlobalFoundries Fotonix 45SPCLO, Tower PH18 — laser is external but everything else is on a single Si die); (b) discrete TOSA / ROSA (legacy: hermetically sealed laser+driver and PD+TIA modules in a metal-and-ceramic gold-box assembly; high reliability, high BOM, low integration density); (c) thin-film lithium niobate (TFLN) Mach-Zehnder modulators (HyperLight, Lumiphase, Quantum Computing Inc — ultra-high bandwidth modulator material on a custom platform); and (d) electro-optic polymer modulators (Lightwave Logic, NLM Photonics — extreme bandwidth and low Vπ·L on a polymer-on-Si platform). The Optical Interposer is structurally closer to (b) discrete TOSA/ROSA in being a hybrid assembly, but achieves (a)-class integration density by using a wafer-scale Si interposer instead of a metal-can package. The competitive thesis is therefore: wafer-scale economics of monolithic SiPh, with the materials freedom of a hybrid build. ⚠ Thesis-level framing; quantitative cost-per-bit comparison not yet primary-sourced.

POET’s commercial productization stack as of mid-2026 includes the POET Infinity family (chiplet-based 400G-lane building blocks that scale to 800G, 1.6T, 3.2T) and the POET Teralight family (cost-and-performance-optimized 1.6T optical engines). The most current technical hero unit is the Hybrid-Integrated 1.6T 2xFR4 transmitter PIC demonstrated at ECOC 2025, which integrates four 2×200G EML arrays + eight high-speed driver ICs + two arrayed-waveguide-grating MUX on a single Optical Interposer substrate. ✓ (ECOC 2025 technical paper)

1. Architecture — the Optical Interposer stack

1.1 The substrate: passive silicon waveguide layer

The Optical Interposer is fabricated on 8-inch silicon wafers at SilTerra Sdn Bhd in Kulim, Malaysia, using a custom POET process flow that defines low-loss waveguides, mode-conversion structures, multiplexing elements (arrayed-waveguide gratings — AWGs), and contact / flip-chip pads. ✓ (POET / SilTerra partnership press release, 2018-04-09; confirmed still active in POET FY2024 update, 2025-02-11)

The substrate process is CMOS-compatible, meaning it uses standard semiconductor-fab equipment (lithography, etch, deposition, planarization) and can in principle be ported to any 8-inch silicon foundry that accepts a custom waveguide module. SilTerra is the production-volume partner; POET maintains the recipe IP. ✓ (per technology page disclosure of “advanced semiconductor manufacturing techniques”)

The waveguide design is the single-mode silicon nitride or silicon-oxynitride class typical of low-loss passive Si photonics, optimized for O-band (1310 nm) and C-band (1550 nm) operation that covers the major data-center transceiver wavelength windows (CWDM4, LR4, FR4, DR1/DR4/DR8, ZR). ⚠ Specific waveguide material composition and cross-section dimensions not publicly disclosed; inferred from “passive silicon waveguide” + 8-inch process + AWG MUX integration.

Critical features included on the Interposer substrate per disclosed product photos (POET Infinity blog post, 2023-03-02; 1.6T 2xFR4 PIC, 2025-09):

Single-mode waveguide routes for signal propagation between flip-chip bond pads
Spot-size converters at the III-V chip flip-chip interface to transition from the high-confinement mode of the III-V laser to the low-confinement mode of the Si waveguide
Arrayed-waveguide-grating (AWG) MUX/DMUX monolithically defined in the Si layer, eliminating a discrete MUX component that legacy CWDM4 modules require
High-speed RF transmission lines for sub-100 ps risetime electrical signals between driver IC and modulator
Optical fiber-attach coupling structures at the edge of the Interposer, designed for passive-alignment (no active optical alignment loop) attachment of fiber arrays. ✓ (passive alignment is one of POET’s headline structural claims)

1.2 The active layer: flip-chip bonded III-V and CMOS

On top of the passive substrate POET flip-chip bonds:

III-V active photonic devices — lasers (DFB, EML), photodiodes (PD, APD), and external modulators where used. The lasers are typically electro-absorption-modulated lasers (EMLs) for the 200G-per-lane PAM4 generation, sourced from external III-V suppliers including Mitsubishi Electric (400G EMLs into POET 1.6T engines per POET 2024 disclosure), Almae Technologies (an Accelink-affiliated InP epi house, June 2018 collaboration), and Sivers Semiconductors (high-power DFB lasers for external-light-source modules, Sept 2025 collaboration)
CMOS electronic ICs — modulator drivers, transimpedance amplifiers (TIAs), MUX/DMUX retimers, DSPs (where co-located on the engine vs. on the host module). Driver ICs come from external silicon-foundry-sourced partners; receiver-side TIAs include the Semtech FiberEdge 200G-per-lane family integrated into POET’s 1.6T receiver engines per the October 2025 Semtech collaboration. ✓

The flip-chip step is performed by POET in-house (process-IP-protected) and at the SPX Xiamen and Globetronics Penang back-end facilities (Globetronics 2024-12-23). The flip-chip alignment is what differentiates POET’s process from a “standard” hybrid SiPh approach: the Interposer carries fiducial marks and pad geometries that allow passive alignment (mechanical-tolerance-driven) rather than active alignment (real-time photocurrent-feedback driven), which is a major cycle-time and cost driver in datacom packaging. ✓ (passive alignment is highlighted in the POET technology page as a hallmark feature)

1.3 Packaging and form-factor outputs

The Interposer-plus-actives assembly is itself an optical engine — a chip-scale subsystem that an OEM module-maker can drop into a pluggable transceiver cage (QSFP-DD, OSFP, OSFP-XD) or onto a CPO substrate adjacent to a switch ASIC. POET’s customers (transceiver-module makers like Mentech, Lessengers; design-services partners like Foxconn Interconnect Technology, Luxshare; and direct end-customers including Semtech for receivers) build the surrounding plastic/metal housing, the host PCB, and the optical fiber connector. POET ships an engine, not a complete transceiver. ✓ (per POET 2024-12-23 Globetronics agreement, POET defines the design exclusively and contracts assembly only)

The implication for unit economics: POET captures the engine ASP (estimated $50–$200 per engine for 800G–1.6T classes, ⚠ inferred from the $5.0M / $5.6M production-order disclosures translated against typical 800G transceiver volumes of tens of thousands of units), not the full transceiver ASP ($500–$2,000 for current 800G, $1,500–$5,000 for 1.6T). Margin on POET’s side is structurally higher per unit-of-engine because the high-cost III-V epitaxy is value-passed-through, but the addressable revenue per port is lower than a full-stack module-maker’s.

2. Comparison vs. competing platforms

2.1 vs. monolithic silicon photonics (Intel SiPh, GF Fotonix 45SPCLO, Tower PH18)

Monolithic SiPh integrates everything except the laser onto a single silicon die: waveguides, modulators (Mach-Zehnder or ring), photodiodes (germanium-on-Si), and sometimes the driver/TIA in monolithic SiGe-BiCMOS. The laser is external (a “comb laser” or external light source — ELS — chip is bonded or fiber-coupled in).

Where monolithic SiPh wins:

Higher yield at very high integration density because there are no flip-chip alignment steps for modulator and PD ✓
Lower per-unit packaging cost at scale because the modulator+PD+driver are in a single die ✓
Foundry-fungible — multiple SiPh foundries (Intel, GF Fotonix, Tower PH18, IMEC, AIM Photonics) compete for capacity ✓

Where the POET Interposer wins:

Modulator material freedom. The active device on the POET interposer is whatever the III-V supplier provides — high-extinction-ratio EMLs from Mitsubishi, ultra-fast TFLN modulators from QCi (per the Nov 2025 3.2 Tbps collaboration), or future EO-polymer modulators. Monolithic SiPh is locked to the silicon Mach-Zehnder modulator’s intrinsic Vπ·L–bandwidth tradeoff. ✓
Direct-modulation laser path. Si MZ modulators require an upstream CW laser; EMLs on the POET platform combine the laser and modulator in one InP chip, simplifying the photonic chain and eliminating a coupling loss. ✓
Higher modulator efficiency. InP EMLs at 200G/lane are well-established and have demonstrated production yields; monolithic Si MZM at 200G/lane PAM4 is just hitting volume and remains thermally and power-efficiency-challenged. ◐ (industry consensus per OFC 2025/2026 program; POET’s specific demonstration is in the ECOC 2025 1.6T 2xFR4 paper)

Where the POET Interposer is not an obvious win:

POET still depends on flip-chip alignment, which is a yield drag relative to a fully monolithic die. The “passive-alignment” claim mitigates but does not eliminate this. ⚠
POET does not own its laser supply, so it inherits the III-V industry’s pricing and capacity dynamics — particularly tight for InP EMLs at 200G/lane through 2026–2027. ◐ (per industry capacity commentary; see POET 1.6T 2xFR4 blog post noting “EML array (an industry first), which results in a dramatic capacity increase of Indium Phosphide-based EML lasers at a time when the industry is facing shortages”)

2.2 vs. discrete TOSA / ROSA (legacy)

Discrete TOSA/ROSA is the legacy datacom architecture: a hermetically sealed gold-and-ceramic can (“box”) containing one or more lasers, drivers, modulators, multiplexers; coupled by short fiber pigtails to the host PCB and the front-panel fiber. Reliability and qualification heritage are extreme (telecom Bellcore standards run 30+ years), but BOM and footprint are uncompetitive for >800G port density.

POET’s structural advantage: 5–10× cost reduction and 5–10× footprint reduction vs. discrete TOSA/ROSA at the same port-rate ⚠ (order-of-magnitude estimate; actual ratio depends on volume and module type). The wafer-scale Si interposer eliminates the gold-can package, the discrete MUX, and most of the wire bonds. POET highlights “elimination of wire bonds” and “passive assembly of components” as headline features. ✓ (per POET 2022-10-27 press release)

Where discrete TOSA/ROSA still wins: very long telecom outside-plant qualification cycles (where the 30-year reliability heritage matters more than cost), and certain low-volume specialty modules where the NRE for a custom Interposer mask set is uneconomic.

2.3 vs. thin-film lithium niobate (TFLN — HyperLight, Lumiphase, Quantum Computing Inc)

TFLN uses a thin film of lithium niobate (a strong electro-optic crystal) bonded to a silicon-on-insulator wafer to build extremely high-bandwidth Mach-Zehnder modulators. Demonstrations >100 GHz EO bandwidth are routine; sub-1 V Vπ·L figures of merit are achievable. The platform is in early production through HyperLight and Lumiphase.

Where TFLN wins: raw EO bandwidth and Vπ·L; relevant for 400G/lane PAM4 (3.2T/port) and beyond, and for coherent ZR/ZR+/ZR2 modulators where high modulation depth at low drive voltage matters. ✓

POET’s posture vis-à-vis TFLN: complementary, not competitive. The Nov 2025 collaboration with Quantum Computing Inc explicitly integrates QCi’s TFLN modulators onto the POET Optical Interposer, producing a 3.2 Tbps optical engine targeted for completion in H2 2026. POET is positioning the Interposer as the integration substrate that lets TFLN modulators be flip-chip-attached alongside lasers and drivers in a single packaged engine — which TFLN-only vendors otherwise cannot deliver. ✓ (QCi-POET press release 2025-11-11)

This is a meaningful strategic point: POET converts the TFLN players from threats into customers / partners by being the packaging layer their modulator chiplet plugs into.

2.4 vs. electro-optic polymer (LWLG, NLM Photonics)

EO polymer uses an organic chromophore-doped polymer as the electro-optic material on a silicon-photonic stack-and-slot waveguide. Demonstrated bandwidth runs to >500 GHz with sub-1 V·cm Vπ·L; the material is solution-processable and can be deposited as a thin film at low temperature. Key risk: long-term photochemical and thermal stability of the polymer.

POET’s posture: structurally similar to TFLN — the Optical Interposer can host an EO-polymer modulator chiplet just as it hosts an InP EML. There is no public POET–LWLG or POET–NLM disclosure as of 2026-04-29, but the architectural fit is there. ⚠ Inferred fit; no announced collaboration.

2.5 Summary table — platform comparison

Axis	POET Optical Interposer	Monolithic SiPh	Discrete TOSA/ROSA	TFLN	EO Polymer
Substrate	8” Si (CMOS-compatible)	8” or 12” Si SOI	Metal can + ceramic	TFLN-on-SOI 4-6”	EO-polymer-on-Si
Modulator material	External (InP EML, TFLN, EO-polymer)	Si MZM / ring	InP EML	LiNbO₃	Organic polymer
Laser	External flip-chip InP	External (ELS)	Internal InP	External	External
Driver / TIA	External flip-chip CMOS	Monolithic SiGe BiCMOS or external	External	External	External
MUX/DMUX	Monolithic AWG on Si	Monolithic	External AWG	External	External
Wire bonds	None (flip-chip throughout)	Few (laser only)	Many	Several	Several
Alignment	Passive	Passive (within die)	Active	Mixed	Mixed
Bandwidth ceiling	~200 G/lane (InP EML) → 400 G/lane (TFLN/EO-polymer chiplet)	~100–200 G/lane (Si MZM)	~200 G/lane (InP EML)	>400 G/lane	>500 G/lane
Production volume readiness (2026)	Volume sampling, $5M+ orders	Mass production at multiple foundries	Mass production	Pilot to early volume	Pilot
Materials freedom	High	Low	Low	Medium	Medium
Per-engine cost outlook	Better than TOSA, comparable to monolithic SiPh at scale	Lowest at very high volume	Highest	High (low TFLN volume)	Medium

⚠ Cell entries in the bandwidth-ceiling and cost rows are framework-level; precise per-vendor numbers vary by generation and module type.

3. Structural advantages

3.1 Materials freedom across modulator generations

The single most defensible architectural feature of the POET Interposer is that it can host any flip-chip-compatible electro-optic device. Concretely: the same Interposer mask set can carry an InP EML in the 200 G/lane PAM4 generation (POET Infinity 800G/1.6T), then a TFLN modulator in the 400 G/lane generation (the QCi 3.2 Tbps engine), then a future EO-polymer modulator in the 800 G/lane generation — without re-architecting the substrate. This insulates POET’s platform IP from the eventual winner of the modulator-material race. ✓ (architectural claim; QCi collaboration is the empirical proof point as of Apr 2026)

3.2 Wafer-scale economics and asset-light operating model

POET does not own a fab. Wafer fabrication is at SilTerra (8-inch Si), back-end at Globetronics + NationGate + SPX. CapEx through 2026 has been single-digit to low-double-digit millions ⚠ (per the FY2024 20-F R&D / capex disclosures, accession 0001641172-25-002143). This is ~100× lower than a captive III-V or SiPh fab buildout ($500M–$3B for a green-field photonics line per industry comparables), and lets POET scale revenue without scaling balance sheet. ✓

3.3 Integration density relative to discrete

POET’s 1.6T 2xFR4 Transmitter PIC integrates four 2×200G EML arrays, eight high-speed driver ICs, and two AWG multiplexers on a single substrate (per the ECOC 2025 paper). That’s roughly 14 active+passive components consolidated from what would otherwise be a 30+ component PCB-level assembly in a discrete TOSA-based 1.6T module. ✓

3.4 Passive-alignment cycle time

Passive alignment of fiber arrays and III-V chips means assembly is dominated by mechanical-tolerance pick-and-place rather than real-time optical feedback. Cycle times approach standard semiconductor assembly (sub-second), versus active-alignment cycles measured in tens of seconds. ⚠ Order-of-magnitude framing; precise cycle-time benchmark is not publicly disclosed.

4. Structural limitations and risk

4.1 III-V supply dependency

POET’s optical engines are only as fast as the III-V devices flip-chipped onto them. The 1.6T 2xFR4 transmitter requires 200 G/lane EMLs, which are in industry-wide tight supply through 2026 per POET’s own Sept 2025 commentary about “a dramatic capacity increase of Indium Phosphide-based EML lasers at a time when the industry is facing shortages.” ✓ Sourcing relationships with Mitsubishi Electric, Almae/Accelink, and Sivers Semiconductors mitigate single-supplier risk but do not eliminate the structural dependency on the III-V industry’s capacity ramp.

4.2 Flip-chip yield

Despite passive alignment, flip-chip bonding still introduces a yield-loss step relative to fully monolithic SiPh. Quantitative POET-specific yield data is not publicly disclosed. ⚠ Industry benchmarks for high-density photonic flip-chip run 90–98% per-bond yield; for an engine with 14 active/passive components, compounded yield can be a meaningful drag.

4.3 Customer concentration and order reversibility

The April 23 2026 Marvell-Celestial AI cancellation of all POET purchase orders — citing alleged confidentiality breaches — is the highest-profile reminder that disclosed engagements can reverse. Per POET 2026-04-27 disclosure, the cancelled orders were originally disclosed 2023-04-25 as production-unit purchase orders. POET’s stock fell 46% on the news. ✓ Customer concentration risk is structural for a small-cap platform-IP company with a handful of engagements.

4.4 Standards-body absence

POET as a small-cap company is not a voting member of OIF or IEEE 802.3 in the way that Marvell, Broadcom, Cisco, Coherent, and Lumentum are. Standards-body influence at 1.6T and 3.2T is significant — and is indirectly accessed through partnerships (Semtech, Sivers, Mitsubishi Electric, FIT, Luxshare) rather than directly. ⚠ Inferred from public membership rosters; specific committee participation by POET technical staff not separately verified.

4.5 NRE-versus-volume break-even

A custom Interposer mask set is expensive (NRE in the seven-figure range per platform variant ⚠) and requires tens of thousands of units to amortize. Module variants with annual volumes below that NRE break-even (e.g., specialty telecom, DCI long-haul tunables) remain uneconomic on the POET platform vs. discrete builds — limiting addressable market mix.

5. Where the platform fits in the data-center optical stack

The data-center optical layer can be partitioned into:

Switch ASIC (Broadcom Tomahawk, Marvell Teralynx, Cisco Silicon One, NVIDIA Spectrum-X) — not POET addressable
Switch-side SerDes / optical engine (CPO substrate or pluggable cage) — POET addressable
Pluggable transceiver module (QSFP-DD / OSFP / OSFP-XD) — POET addressable at the engine layer
Active optical cable / AEC (Credo, Astera) — not POET addressable
Optical line cards (long-haul DCI, ZR/ZR+/ZR2) — POET addressable on the modulator side via the QCi TFLN partnership ✓

Within “POET addressable”: the immediate ramp is 800G FR4/DR8/2xFR4 and 1.6T 2xFR4/DR8 pluggable optical engines for AI cluster networks, and the medium-term opportunity is 3.2T CPO and external-light-source (ELS) modules addressed by the Sivers and QCi partnerships.

6. Cross-references

Optical interconnect roadmap — generation-by-generation mapping of POET products against industry standards
Products — current SKUs (POET Infinity, POET Teralight, 1.6T 2xFR4 PIC, etc.)
Foundry relationships — SilTerra, Globetronics, NationGate, SPX details
DenseLight acquisition — pre-history of POET’s III-V capability
competitors — head-to-head positioning vs. monolithic SiPh, TFLN, EO polymer, discrete TOSA/ROSA players
partners — Mitsubishi Electric, Almae/Accelink, Sivers, Semtech, QCi, FIT, Luxshare, Globetronics, NationGate